Sharp-switching Top-gated Indium-zinc-oxide Thin Film Transistors Using a Novel
in-
situ
Dielectric Formation Process
David C. Paine
1
, Yang Song
2
, Alexander Zaslavsky
1,2
, and Alexander Katsman
1
Brown University, School of Engineering, 182 Hope St, Providence, RI 02912, USA
2
Brown University, Dept. of Physics, 182 Hope St, Providence, RI 02912, USA
3
Technion, Dept. of Materials Science and Engineering, Technion City, Haifa, Israel
E-mail address of presenting author:
Amorphous oxide semiconductor (AOS) thin film transistors (TFT’s) offer many now-well-known
advantages for display TFT applications. Other applications of amorphous oxide electronic materials
have been slow to emerge despite the possibilities presented by relatively high mobility (10-50 for
IZO vs. 0.1-1 cm
2
/Vsec for Si), room temperature processing, high surface planarity, and isotropic
etch characteristics. We have investigated the use of Indium zinc oxide (IZO) and buried reactive
metal layers to create high concentration doping profiles and, simultaneously, buried dielectrics
formed by
in-situ
solid state reaction between selected metals and a-IZO.
The method relies on the
deposition of substoiciometric oxides or pure metals that are thermodynamically unstable on
IZO. Simple low temperature annealing results in a local interfacial reaction that results in
the chemical reduction of IZO (creating oxygen vacancies, a defect donor) and the oxidation
of the reactive over-layer to create high quality dielectrics and interfaces. We have recently
demonstrated [1] a top-gated IZO TFT synthesized with a thin deposited 3 nm Al layer
between the 10 nm thick IZO channel and 24 nm HfO
2
gate insulator. A 300
o
C anneal was
used to convert Al
in-situ
into Al
2
O
3
, resulting in a passivated Al
2
O
3
/HfO
2
gate stack.
Similarly, a high quality reacted oxide gate interface was formed using substoiciometric
deposited HfO
2-x
deposited using e-beam evaporation followed by post processing annealing
at 300
o
C.
Both types of dielectric formation yield TFTs of gate length L G = 50 µm with
excellent characteristics. The Al
2
O
3
/HfO
2
gate stack TFTs, annealed for 8 hours, show a low
interface trapped charge density N
TC
~ 7.2×10
11
cm
-2
(extracted from C–V
G
measurements),
high on/off current ratio of ~10
7
, sharp subthreshold slope of ~0.14V/decade, a low threshold
voltage V
T
= 0.23 V, and a low-field mobility µ
0
~ 135 cm
2
/V*s. The simpler HfO
2
TFTs,
annealed for 4 hours, have even better characteristics: lower N
TC
~ 2.3×10
11
cm
-2
, similar
on/off current ratio ~10
7
, improved near perfect subthreshold slope of ~0.065 V/decade, V
T
= –0.02 V, and low-field mobility µ
0
~ 95 cm
2
/V*s. When implemented in top-gated TFTs
with submicron L
G
, these in-situ dielectrics promise unparalleled performance in the oxide
transistor arena.
In addition, we have attacked several critical a-IZO materials challenges that
limit these applications including low-resistance metal/IZO contacts, high and stable carrier
density channels, and integration of materials with high dielectric constants. The
development of new electronics applications based on AOS materials in general, and IZO in
particular, is also limited by the absence of a knowledge of even relatively fundamental
properties such as the coefficient of thermal expansion, diffusivity of oxygen, pseudo-
equilibrium carrier density, dependence of mobility on carrier density, and amorphous oxide
structural stability. In this talk, new work in theses areas will be presented.
[1]
Y. Song, R. Xu, J. He, S. Siontas, A. Zaslavsky, and D. C. Paine,
IEEE Electron Device Lett.
, 35 (2014)
1251-1253
I 13
-95-
